This invention relates to an interface apparatus and frequency-fluctuation test method in a network in which data to be transmitted is assembled into a fixed-length cell and then sent. More particularly, the invention relates to an interface apparatus and frequency-fluctuation test method through which a test for fluctuation in frequency can be performed by a simple arrangement.
B-ISDN (broadband-ISDN) switching technology, which is based upon the asynchronous transfer mode (ATM), is being put to practical use as a means for realizing broadband communication.
FIGS. 6A to 6D illustrate B-ISDN system configurations, in which only ATM cells that travel from right to left are shown. In actuality, however, ATM cells travel in both directions. FIG. 6A shows a configuration in which ATM terminals 12, 13 are connected to an ATM switch 11 and communication between the ATM terminals is performed by ATM cells via the ATM switch 11. In these figures, UNI signifies a user network interface. FIG. 6B shows a configuration in which various user terminals 14, 15 are connected to ATM terminals 12, 13, respectively. The ATM terminals 12, 13 convert data from the user terminals to ATM cells and then send the ATM cells to the side of the ATM switch 11, and convert ATM cells received from the ATM switch 11 to data for the user terminals and then send the data to the user terminals. FIG. 6C shows a configuration provided with interworking function units (IWFU) 18, 19 that provide a function for interworking with other networks (e.g., frame relay networks) 16, 17, respectively. FIG. 6D shows a configuration in which the ATM switch 11 internally accommodates an interface converter 11a and performs an internal conversion between the data of another network and ATM cells.
A B-ISDN of the above-described type affords a service through which user data is sent at a constant rate. This is a CBR (Constant Bit Rate) service. With the CBR service, the timing of a user clock on the receiving side (i.e., the receiving user clock) must be made to coincide with the timing of the user clock on the sending side. If the user clock on the sending side is synchronized to the clock of the network, the timings of the user clocks on the sending and receiving sides can be made to agree by generating the receiving user clock from the network clock on the receiving side.
However, there are instances where the timing of the user clock [1.544 Mbps at DS1 (Digital Signal Level 1) and 44.736 Mbps at DS3 (Digital Signal Level 3), which are standardized in the G.700 series of DS recommendations of the ITU] on the sending side is not in sync with the timing of the network clock on the network side. For example, there are cases where the user terminals 14, 15 in the configuration of FIG. 6B send user data using internal clocks of their own, and cases where the network clocks of the networks in FIGS. 6C and 6D differ from the network clock of the ATM network. Even if the nominal value of the frequency of the sending user clock is known and the receiving side generates a receiving user clock having the same nominal value by frequency dividing the network clock (an example of which is 155.56 MHz), a timing error develops between the sending user clock and the receiving user clock, a consequence of which is that a faithful CBR service cannot be provided.
The SRTS (Synchronous Residual Time Stamp) method has been proposed as a method of synchronizing the receiving user clock to the sending user clock. The SRTS method incorporates timing information of the sending user clock in an ATM cell on the sending side, extracts this timing information of the sending user clock from on the receiving side and synchronizes the receiving user clock to the sending user clock based upon the timing information extracted. In order to send the timing information of the user clock, use is made of AAL-1 (ATM Adaptation Layer-1) standardized as an ATM cell by DS recommendation I.363, etc., of the ITU.
FIG. 7 is a diagram useful in describing the format of an AAL Type-1 (AAL-1) ATM cell, and FIG. 8 is a diagram useful in describing the format of a 1-byte SAR-PDU header. In the AAL-1 ATM cell, a 48-byte information field is composed of an SAR-PDU payload having a length of 47 bytes and an SAR-PDU (PDU is the abbreviation of Protocol Data Unit) having a length of one byte. The 47-byte SAR-PDU payload is used to transfer user data. The 1-byte SAR-PDU header is composed of a 4-bit SN (Sequence Number) field and a 4-bit SNP (Sequence Number Protection) field.
The SN field is subdivided into two subfields, namely CSI (Convergence Sublayer Identifier) and SC (Sequence Count) subfields, and so is the SNP field, namely CRC (Cyclic Redundancy Check) and EPB (Even Parity Bit) subfields. The SC subfield counts cells cyclically from 1 to 8 (i.e., 1, 2, . . . , 8, 1, 2, . . . , 8, 1, . . . ) and makes it possible to monitor the sequence of the cells. Error detection and correction of the sequence number (SN) is performed by the CRC and EPB subfields. The CRC is a value based upon a polynomial (G(X)=X3+X+1) with respect to the sequence number. The EPB is an even-numbered parity bit in the SAR-PDU header. The CSI bit is the CS (Convergence Sublayer) function of the AAL-1 ATM cell and is used to send and reproduce the timing information of the user clock in a manner described below.
In accordance with the SRTS method, the timing information of the user clock is composed of 4-bit information (RTS4, RTS3, RTS2, RTS1) referred to as an RTS (Residual Time Stamp). This RTS information is transferred by the CSI bit, which is the CS function of the AAL-1. FIG. 9 is a diagram for describing the format of the RTS information. The RTS information format is a multiframe format for eight ATM cells. Since the user data is transferred by the SAR-PDU payload, the number of bits of user data in eight ATM cells is 3008 bits (8 cellsxc3x9747 bytesxc3x978 bits).
The CSI bit has an 8-bit structure (CSI0 to CSI7) corresponding to SC (Sequence Count) values of 0 to 7, respectively. Four-bit RTS information is sent by CSI bits (CSI1, CSI3, CSI5, CSI7) of ATM cells whose SC values are 1, 3, 5, 7. In other words, RTS4 is transferred by an ATM cell whose SC value is 1, RTS3 by an ATM cell whose SC value is 3, RTS2 by an ATM cell whose SC value is 5, and RTS1 by an ATM cell whose SC value is 7.
FIG. 10 is a diagram useful in describing the RTS-information generating cycle. In accordance with the CBR service, sending user data DTU is data having a constant speed, and a clock synchronized to this data is a sending user clock CTU in FIG. 10. In an ATM cell, the information of the sending user data DTU is transmitted by the SAR-PDU payload, and the RTS information, which is the timing information of the sending user clock CTU, is transmitted by the CSI bit. Consequently, the RTS-information generating cycle TTS is equal to TTUxc3x973008, where fTU represents the frequency of the sending user clock and TTU (=1/fTU) represents the time equivalent to one bit of the user data. Let the clock for generating the RTS data be a transmission RTS sampling timing clock CTS. In such case the RTS information is generated at the rising edge of the clock CTS, and the transmission RTS sampling timing clock CTS is obtained by frequency dividing the sending user clock to 1/3008.
In the SRTS method, the network clock frequency fN (an example of which is 155.56 MHz) synchronized to the line timing on the network side is frequency divided to generate a network frequency-divided clock CNX (frequency fNX=fN/2X, where 1/2X represents the frequency dividing ratio). The frequency dividing ratio 1/2X is decided in such a manner that the ratio of the network frequency-divided clock frequency FNX to the nominal value fNOM of the user clock frequency will fall within the range 1xe2x89xa6(fNX/fNOM) less than 2.
Next, the network frequency-divided clock frequency fNX is frequency divided by a 4-bit binary counter to generate network timing information Q1, Q2, Q3 and Q4 having frequencies fNX/21, fNX/22, fNX/23 and fNX/24, respectively. Values obtained by sampling the network timing information Q1, Q2, Q3, Q4 at the rising edge of the transmission sampling clock CTS become RTS1, RTS2, RTS3, RTS4, respectively. This is the RTS information.
The formats for generating and transmitting the RTS information are specified in the international recommendations as set forth above.
FIG. 11 is a diagram showing the construction of an RTS generating and transmitting unit in a case where the transmission RTS information is created and transmitted in accordance with the international recommendations.
An ATM cell disassembler 20 extracts and outputs a network clock CN (frequency fN, an example of which is 155.56 MHz), which is contained in an ATM cell RATM received from an ATM network, by a PLL (Phase-Locked Loop). A network clock frequency divider 21 frequency divides the network clock CN, which has been synchronized to the line timing on the network side, thereby outputting the network frequency-divided clock CNX. In this case the network clock frequency divider 21 frequency divides the network clock by 2X (where X is an integer) in such a manner that the ratio of the network frequency-divided clock frequency FNX to the nominal value FNOM of the user clock frequency will fall within the range 1xe2x89xa6(fNX/fNOM) less than 2. For example, in DS1transmission, the nominal value FNOM of the sending user clock frequency is 1.544 MHz. If the network clock frequency fN is 155.56 MHz, therefore, we have X=6 and the network frequency-divided clock frequency fNX becomes 155.56 MHz/26, which is equal to 2.43 MHz. Similarly, in DS3 transmission, X=1 holds and we have fNX=155.56 MHz/2=77.78 MHz.
Next, a 4-bit binary counter 22 counts the network frequency-divided clock CNX and outputs the network timing information Q1, Q2, Q3, Q4 of frequencies fNX/21, fNX/22, fNX/23, fNX/24 from respective ones of four stages.
Meanwhile, a transmission frequency-dividing counter 23 frequency divides, by 3008, the sending user clock CTU (of frequency fTU) synchronized to the sending user data DTU, and outputs the transmission RTS sampling clock CTS (of frequency fTS=fTU/3008).
A transmission RTS generator 24 samples the network timing information Q1, Q2, Q3, Q4 at the rising edge of the transmission RTS sampling clock CTS and outputs the result as transmission RTS information TRTS1, TRTS2, TRTS3, TRTS4. If the frequency fTU of the sending user clock CTU fluctuates, the rising-edge timing of the transmission RTS sampling clock CTS fluctuates and, hence, so does the value XH of the transmission RTS information TRTS1-TRTS4. In other words, the transmission RTS information includes the timing information of the sending user clock CTU.
An ATM cell assembler 25 uses the sending user data DTU, the sending user clock CTU synchronized thereto and the transmission RTS information that enters from the transmission RTS generator 24 to assemble eight ATM cells TATM for every 3008xc3x97TTU, and sends these ATM cells to the ATM network in sync with the network clock CN (fN=155.56 MHz).
FIG. 12 is a block diagram showing a receiver that generates the receiving user clock synchronized to the sending user clock using the RTS information. The receiver includes a receiving user clock adjustment unit 70; an internal RTS information generator 71 for generating internal RTS information IRTS1-IRTS4, which is the timing information of a receiving user clock CRU, and a reception RTS sampling clock CRS synchronized to the internal RTS information IRTS1-IRTS4; an arithmetic unit 72 for calculating the difference between RTS information (called the reception RTS information but actually transmission RTS information sent from the sending side) RRTS1-RRTS4, which is contained in an ATM cell that has been sent from the sending side, and the internal RTS information IRTS1-IRTS4; a receiving user clock generator 73, which is constituted by a PLL, for adjusting and outputting the timing of the receiving user clock CRU in such a manner that the above-mentioned difference will become zero; and an ATM cell disassembler 81 for extracting the network clock CN from an ATM cell received from the ATM network, inputting this clock to the internal RTS information generator 71, disassembling a received ATM cell into user data DRU and RTS information RRTS1-RRTS4, and outputting the same.
The internal RTS information generator 71 uses the frequency of the network clock CN and the frequency of the receiving user clock CRU to generate the internal RTS information IRTS1 to IRTS4, which is the timing information of the receiving user clock CRU, and the reception RTS sampling clock CRS synchronized to this information.
As shown in FIG. 13, the internal RTS information generator 71 has a network-clock frequency divider 71a, a 4-bit binary counter 71b, a reception frequency-dividing counter 71c and an internal RTS information generator 71d. The network-clock frequency divider 71a frequency divides the network clock CN by 2X (where X is an integer). The 4-bit binary counter 71b counts the network frequency-divided clock CNX (the frequency of which is fNX) and outputs the network timing information Q1, Q2, Q3, Q4 of frequencies fNX/21, fNX/22, fNX/23, fNX/24 from respective ones of four stages. The reception frequency-dividing counter 71c frequency divides, by 3008, the receiving user clock CRU (of frequency fRU) and outputs the reception RTS sampling clock CRS (of frequency fRS=fRU/3008). The internal RTS information generator 71d samples the network timing information Q1, Q2, Q3, Q4 at the rising edge of the reception RTS sampling clock CRS and outputs the result as the internal RTS information IRTS1, IRTS2, IRTS3, IRTS4.
The arithmetic unit 72 calculates the difference between the internal RTS information IRTS1-IRTS4 and reception RTS information (the transmission RTS information sent from the sending side) RRTS1-RRTS4, and the receiving user clock generator 73 adjusts and outputs the timing of the receiving user clock CRU in such a manner that this difference will become zero. As a result, the timing (frequency and phase) of the receiving user clock CRU can be made to agree with the timing of the sending user clock CTU. The ATM cell disassembler 81 extracts and outputs the network clock CN from an ATM cell received from the ATM network, outputs the user data DRU in sync with the receiving user clock CRU that enters from the receiving user clock generator 73, and outputs the reception RTS information RRTS1-RRTS4 in sync with the reception RTS sampling clock CRS.
To sum up, DS1 or DS3 PCM transmission data is converted to the ATM cell format of AAL-1 (ATM Adaptation Layer-1) and the cell is then sent via an ATM network. This is done on the sending side. On the receiving side, the receiving clock CRU, which is synchronized to the frequency of the transmitting clock, is generated and data is output in sync with this receiving clock.
The function through which DS1, DS3 PCM transmission lines interwork with an ATM switch is referred to as a circuit emulation (CE) function.
FIG. 14A shows the system configuration in a case where the DS3 PCM transmission line interworks with an ATM switch by way of ATM interface units having a CE function. FIG. 14B is a diagram useful in describing the layer of each unit. Shown in FIG. 14A are an ATM switch (ATM SW) 51, terminals (CPE) 52, 53, DS3 PCM transmission paths, and ATM interface units (DS3 CE INF) 56, 57 having the CE function.
The transmitting sections of the ATM interface units 56, 57 map the data having the DS3 frame format, which data arrives from the PCM transmission path, to the payload of the AAL-1 (ATM Adaptation Layer-1) cell of FIG. 7, incorporates the timing information (transmission RTS information) of the user clock in the CSI bit of the SAR header and then sends the resulting signal to the ATM switch. The receiving sections of the ATM interface units 56, 57 synchronize the receiving user clock to the sending user clock using the transmission RTS information included in the ATM cell, convert the ATM cell to the DS3 data and send the data to the DS3 PCM transmission path.
In a communication scheme wherein this frequency information (RTS information) is transmitted, confirming the fact that the frequency information is being transmitted reliably and verifying trackability with respect to fluctuations in frequency must be included as test items that are always checked in order to maintain reliability of communication.
However, it is not easy to vary frequency on a communication line, a multifunctional tester or dummy terminal must be connected to the opposite unit and a high-performance oscitllator is required to be connected. FIG. 15 illustrates a testing set-up according to the prior art. Shown in FIG. 15 are the ATM switch (ATM SW) 51, ATM interface units (ATM Inf) 56, 57 having the CE function, test measurement devices 61, 62 connected to the interface units 56, 57, respectively and frequency varying high-performance oscillators 63, 64 connected to the measurement devices 61, 62, respectively.
In order to test for a fluctuation in frequency, the oscillator 63 connected to the measurement device 61 outputs a clock to which the necessary fluctuation in frequency has been applied. The measurement device 61 sends DS1 or DS3 PCM data to the ATM interface unit 56 by PCM transmission. The ATM interface unit 56 maps the PCM data, which has been received from the measurement device 61 via the PCM transmission line, to the payload of the ATM cell of AAL-1 type, creates frequency information (RTS information), incorporates this information in the CSI bit of the SAR header of the ATM cell and then sends the resulting signal to the opposite unit via the ATM switch 51.
The opposite ATM interface unit 57 extracts the frequency information (RTS information) from the received ATM cell, generates a receiving clock based upon the RTS information and sends the PCM data to the measurement unit 62 in sync with the receiving clock. The measurement unit 62 measures the frequency of the received PCM data, determines absence or presence of a bit error, confirms transmission of the frequency information and verifies tracking of a fluctuation in frequency. In order to conduct a test in the opposite direction, the oscillator 64 connected to the measurement unit 62 outputs a clock to which the necessary frequency fluctuation has been applied.
The measurement units 61, 62 are primarily comparatively small, high-performance devices, but the oscillator, which has a precision needed to evaluate the fluctuation in frequency, is large in size and high in cost. Consequently, testing of frequency fluctuation can be performed by the manufacturer when the apparatus is shipped but on-site adjustment after shipping is impossible in terms of the facilities available.
Accordingly, an object of the present invention is to provide an interface apparatus and frequency-fluctuation test method in which a testing oscillator can be dispensed with and a test of frequency fluctuation can be conducted easily through a simple arrangement.
Another object of the present invention is to provide an interface apparatus and frequency-fluctuation test method in which a opposite station apparatus and own apparatus can be subjected to a frequency-fluctuation test through a simple arrangement.
According to a first aspect of the present invention, the foregoing objects are attained by providing an interface apparatus the transmitting section of which comprises (1) first transmission-timing information generating means for generating transmission timing information, which constitutes timing information of a sending user clock, using a network clock and the sending user clock, which is synchronized to sending user data, (2) second transmission-timing information generating means for generating test transmission timing information, (3) a selector for selecting the transmission timing information, which is output by the first transmission-timing information generating means, during ordinary communication, and for selecting the test transmission timing information during a test, and (4) cell assembling means for assembling the sending user data and the transmission timing information selected by the selector into a fixed-length cell and sending the cell to a network.
If the phase and frequency of the sending user clock change, the transmission timing information (transmission RTS information) varies. When the transmission timing information varies, the receiving station controls the timing (phase, frequency) of the receiving user clock to make this timing agree with the timing of the sending user clock, reads out data in sync with this receiving user clock and transmits the data. This means that if the transmission timing information is changed, the receiving-station side regards this as signifying a variation in the sending user clock, even though the timing (phase, frequency) of the sending user clock has not actually varied, and proceeds to change the timing of the receiving user clock. Accordingly, if the transmission timing information is altered without changing the sending user clock when a test is conducted on the side of the receiving station, and a variation in the timing of the receiving user clock or a bit error is monitored on the receiving-station side, then it is possible to test for a fluctuation in frequency.
More specifically, the transmitting section of the interface apparatus generates transmission timing information for testing purposes, assembles the sending user data and the test transmission timing information into a fixed-length cell when a test is conducted, and transmits the cell to the opposite station apparatus via a network. The opposite station apparatus monitors the timing of the receiving user clock, thereby conducting the test for frequency fluctuation.
According to a second aspect of the present invention, the foregoing objects are attained by providing an interface apparatus the receiving section of which comprises (1) a cell disassembler for disassembling a cell received from a network into user data and reception timing information and outputting the user data in sync with a receiving user clock, (2) timing information generating means for generating test reception timing information, (3) a selector for selecting the reception timing information, which is output from the cell disassembler, during ordinary communication, and selecting the test reception timing information during a test, (4) means for generating internal timing information, which constitutes timing information of the receiving user clock, using a network clock and the receiving user clock, and (5) receiving user clock generating means for adjusting and outputting the timing of the receiving user clock in such a manner that a difference between the internal timing information and the reception timing information selected by the selector will become zero.
If the reception timing information is altered, even though the phase and frequency of the sending user clock actually do not change, the receiving-station side regards this as signifying a variation in the sending user clock and proceeds to change the timing of the receiving user clock, just as in the first aspect of the present invention. Accordingly, by altering the reception timing information and monitoring the timing of the receiving user clock or bit error when own apparatus is tested, a frequency tracking test of its own apparatus is conducted. More specifically, the receiving section of the interface apparatus generates reception timing information for testing purposes, controls the timing of the receiving user clock in such a manner that the difference between the internal timing information and the test reception timing information becomes zero when a test is conducted, and monitors the timing of the receiving user clock to thereby conduct the test for frequency fluctuation.
Further, the foregoing objects are attained by providing an interface apparatus having the features of both the first and second aspects of the present invention. In this case, the transmission timing information for testing purposes is selected and output when the opposite station apparatus is tested, and the reception timing information for testing purposes is selected and output when its own apparatus is tested. Further, an arrangement may be adopted in which the transmission timing information is generated using a frequency-divided network clock and the sending user clock, and by using different frequency dividing ratios in the case of DS1 and DS3, both DS1 and DS3 can be accommodated.